Duffing Phase-locked Loop: equilibrium and phase jitter
Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, for being the essential element to recover frequency and phase information. Several models and implementation
architectures appeared, following the strong electronic and computation evolution that occurs daily. As modeling and designing work together,
considering the classical phase multiplier architecture, the nonlinearity is replaced by a polynomial approximation, making the differential equation
describing the loop dynamics similar to the classical D"ufing equation. As a result, the new model (D"uffing PLL) presents a robust equilibrium performance and high immunity to accidental frequency modulation (phase-jitter), even for the first-order case, suggesting an interesting alternative implementation of PLLs.